View TRW-HP9M2W_8346716.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 1 wenshing ?? trw - hp9m2w rf module h i p ower 2w 900 mhz transceiver module product description trw - hp9m2w is a high - power wireless radio module. with high - performance transceivers, it can reach its maximum efficiency at very low power consumption. this module is mainly used in the ism (industrial, scientific and medical) and srd (short range device). its frequency band is 902mh z ~928 mhz , and it has a built - in pa. may flexibly adjust the output powe r externally . in ord er to keep abreast of the module in the operating temperature range, you can not only control the output and receive data but also read the rf ic's temperature through the spi control interface. key feature ? frequency range 902mhz~928mhz ? modulation (g)fsk , 4(g)fsk, (g)msk ? max output power 33dbm ? auto frequency control (afc) ? automatic gain control (agc) ? receive sensitivity ? 129dbm ? 60db adjacent channel ? data rate 100 bps to 1 mbps ? temperature sensor ? spi microcontroller interface ? operating temperature - 30~ + 80 application ? amr ? security applications ? wireless metering ? wireless m - bus ? messaging / paging ? remote control ? wireless healthcare ? private mobile radio ? social alarms version history version date changes v1.01 aug. 15 , 2013 1 st. edition
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 2 description trw - hp9m2w rf m odule is high - performance, low - current transceivers covering the sub - ghz frequency bands from 902 to 928mhz. the radios are part of the trw - hp9m2w rf m odule family, which includes a complete line of transmitters, recei vers, and transceivers covering a wide range of applications. all parts offer outstanding sensitivity of ? 129dbm while achieving extremely low active and standby current consumption. the trw - hp9m2w offers frequency coverage in all major bands. the trw - hp9m 2w rf m odule offers frequency coverage in bands not covered by trw - hp9m2w rf m odule family. typically, these are non - standard frequencies or licensed frequency bands. the trw - hp9m2w includes optimal phase noise, blocking, and selectivity performance for na rrow band and licensed band applications, such as fcc part90. the 60 db adjacent channel selectivity with 12.5 k hz channel spacing ensures robust receive operation in harsh rf conditions, which is particularly important for narrow band operation. the trw - h p9m2w rf m odule offers exceptional output power of up to 33dbm with outstanding tx efficiency. the high output power and sensitivity results in an industry - leading link budget of 146 db allowing extended ranges and highly robust communication links. fcc, e tsi, and arib. all devices are designed to be compliant with 802.15.4g and wmbus smart metering standards.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 3 rf ic pll agc osc saw lna front-end module lna rf out ldo spi pe/d power 4v~5.5v tx/rx mode (tx=1 rx =o) gpio3 modem fifo packet handler crc temp frame gan digital logic rf amp control TRW-HP9M2W rf module function block diagram gpio0 1. specification conditions=925mh z vdd =vcc= +5v, vss = 0v, ta = +25oc parameter symbol test condition min typ max unit vol tage range power 5 v power down power power down 2 ua rx mode current receiver 1.8kbps 22.4 ma rx mode current receiver 172kbps 23.3 ma tx mode current transmitter 27dbm( ramp 0.75 voltag e) 730 ma tx mode current transmitter 30dbm( ramp 1 vol tage ) 1100 ma tx mode current transmitter 33dbm( ramp1.8 voltage ) 2000 ma rx sensitivity receiver 1kbps - 126 - dbm this block diagram details the whole structure of this module which allows user to adopt two channels simultaneously wi thout adding any extra components except micro - controller. we shall have reference schematic how this module works with micro - controller in the subsequence.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 4 pin assignments pin name i/o description 1 vcc input +4 to +6 v supply voltage input to internal regulators 2 vcc input +4 to +6 v supply voltage input to internal regulators 3 vcc input +4 to +6 v supply voltage input to internal regulators 4 sclk digital input serial clock input. digital input. this pin provides the serial data clock function fo r the 4 - line serial data bus. data is clocked into the rf chip on positive edge transitions 5 sdo digital output provides a serial readback function of the internal control registers. 6 gpio1 i/o may be configured through the registers to perform various functions including: microcontroller clock output, fifo status, por, wake - up timer, low battery detect, antdiversity control, etc. 7 nsel digital input this pin provides the select/enable function for the 4 - line serial data bus. 8 gnd gnd ground. 9 pe/ d digital input digital input. ped should be = 0 power down 1=power 10 ramp input rf amp control pin (1v to 3.3v control the power. power by the 27dbm to 33dbm, should pay attention to not exceed 3.3v voltage) 12 sdi digital input this pin provides the s erial data stream for the 4 - line serial data bus 13 vdd input +4 to +5.5 v supply voltage input to internal regulators the power supply to the rf chip 14 gnd gnd ground. 15 gnd gnd ground. 16 gnd gnd ground.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 5 2. reference schematics
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 6 3. controller interface 3 .1. serial perip h eral interface (spi) t he trw - hp9m2w com m unicate s wit h th e h os t mc u o v er a s t a n dard 4 - wire serial periph e ral interface ( s pi): sclk, sdi, sdo , an d ns e l. t he spi inte rf ac e i s d e sign ed t o o p e r at e at a m a xim um o f 10 mhz . th e spi t imi n g p a r am e t e r s a r e d em o nst r ate d i n t abl e 8. t he h o s t mc u w r it es d a t a o v er th e sd i pin a nd ca n r ea d dat a f r o m th e devic e o n t he sd o o u t p u t pi n . f i gu re 3 d e mo n st r ate s an s p i w rite c o mma nd. th e n s el p i n s hould go low to init iate the spi command. the fir s t byte of sdi dat a w ill be one of the firmware commands fol l owed by n bytes of p arameter da t a which will be variable depending on t h e s pecific command. the ri s ing edges of s c lk should be aligned with the cen t er of the sdi da t a . t able 8. serial int e rf a ce t iming para m eters s y mbol par a met er mi n ( n s) diag r a m t ch c lock h igh t ime 40 s cl k t ss t c l t c h t d s t d h t d d t s h t de s d i s d o t en t sw n s el t cl clock low time 40 t ds d a t a s e t up time 20 t dh da t a h old time 20 t dd output da t a delay time 20 t en output enable time 20 t de o u t p u t disabl e time 50 t ss select setup time 20 t sh s e le c t ho ld t i m e 50 t sw select high period 80 n s e l s d o s d i s c l k f w c o mm an d p a r a m b y t e 0 p a r a m b y t e n
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 7 f igure 3. spi w r i te comma n d the trw - hp9m2w con t ains an internal mcu which controls all the internal functions of the radio. for spi read commands a typical mcu flow of checking clear - to - send (cts) is used to make sure the int e rnal mcu has exe cuted the command and pre p ared the da t a to be output over the sdo pin. f igure 4 demonstrates the general flow of an spi read command. once the cts value reads ffh then the read da t a is ready to be clocked out to the host mcu. the typical time for a valid f fh cts reading is 20 s. figure 5 demonstrates the remaining read cycle a f ter cts is set to ffh. the internal mcu will clock out the sdo da t a on the negative edge so the host mcu should process the sdo da t a on the rising edge of sclk. firmware flow send command read cts cts value 0xff retrieve response 0x00 nsel sdo sdi sck readcmdbuff cts figure 4. s pi re a d comman d ?ch e ck cts v alue nsel sdo sdi sck respon se byte 0 response byte n figure 5. s pi re a d comman d ? clo c k o u t read da t a
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 8 3 .2. fast r e sponse registers the fast r e spo n se r e gisters are r e gisters that can be r ea d im m edi a t ely w i t h ou t th e r eq u ir e me nt t o mo ni to r and ch e c k cts . t here a r e f o u r f a s t r e s p o n s e r e gist e r s t ha t ca n be p r o g r a mmed fo r a s p ecifi c fu n cti o n. t h e fast r esp o ns e r egiste rs ca n b e r e ad th r ou gh ap i co m ma n ds , 0x50 fo r fas t r e s p o n s e a , 0x 51 fo r f as t res p ons e b, 0 x 53 f or f a s t respo n s e c , a nd 0x5 7 fo r fas t res p ons e d . the fast r e spo n se registers can be configu r ed by the ? f r r _c tl _ x _ mo de? p r o pe rti e s. t he fas t r e spo n s e r e giste rs m a y b e r e a d i n a bu r s t f a s h ion . a f ter the initial 16 clock cycles, each additional eig h t clock c ycles w ill clock out the conten t s of the next fast r e sponse register in a c ircular fashion. the value of the frrs will not be update d unless nsel is toggled. 3 .3. operating modes and t i ming the p r imary s t a t es of the trw - hp9m2w are shown in figure 6 . t h e s h u t d o w n s t at e c o mpl e t e l y s h u t s d ow n th e r a di o to minimize cur r e n t consump t ion. s t andby/ s l e ep, sp i a cti v e, re a d y , t x t u n e , an d r x tun e ar e avail a bl e t o o p timize th e c u r r e nt c o nsum p ti on a n d r esp o ns e tim e t o rx/t x fo r a gi ve n a p p lic a ti o n . ap i c o mma n d s s t a r t _ rx, s t a r t_tx, and change_s t a t e control t h e op e r a t ing s t a t e wi t h t h e e xcep tion of s h u t d o wn w h i c h is c on tr o ll e d by pe/d , pi n t abl e 9 sh o w s e ac h of t he o per atin g m o de s wit h th e tim e r e q ui r e d t o r e ac h ei t h e r r x o r t x m o d e as wel l a s th e cur r e nt c o nsum pt io n o f e a c h m o d e. th e t i me s i n t abl e 9 a re m e asu r e d fr om th e risin g e dg e o f ns el u nti l th e chi p i s i n t he d esir ed s t at e. n o t e th at t h es e tim es are indicative of s t ate transition timing but are n o t guaranteed and should o n ly be used as a refer e nce dat a point. an automatic seq u enc er will put the c h ip into r x or tx from a n y s t ate. it is not n e cessary to manually step thr o ugh the s t ates. t o sim p li fy the dia g r a m it is not sho w n b u t a n y of the lower p o wer s t ates can be r etu r n ed t o auto m atic a ll y a f t er r x or tx. f i gure 6. s t a te m a chine dia g ram
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 9 t able 9 . o p er a ting s t ate response t ime and current consu m ption* fig u re 7 shows the por timing and vol t a g e require m ent s . t h e p o w er c o nsu m ptio n ( b atter y lif e) d e pe n d s on the duty cy c le of the appli c ation or how o f ten the p a rt is in either rx or tx s t ate. in mo s t applications the utilization of the s t andby s t ate w ill be most advan t a g eous for battery life but for very l o w duty c y cle applications shu t do w n will h av e an a d van t a ge . f o r t he fastes t ti mi n g th e n e x t s t at e c an be sel e cte d i n t he s t a r t _ r x or s t a r t_t x api com m ands to minimize spi tra n sactions and internal mcu p r o c e s sing. 3 . 3 . 1. p o w e r o n r e s e t (p o r) a p o we r o n rese t (p or ) seq u e n c e i s u s ed t o b o o t th e d evic e up from a fully o f f or shu t down s t ate. t o execu t e this p r o c e ss , vd d mus t r a mp wit hin 1m s a nd m u s t r e mai n ap p lie d t o th e d evic e f or at le a st 100 ms . i f vd d i s r em o v e d, then i t must s t ay b e low 0.15v for at l east 1 0 ms b e fore b ei ng a p p lie d a g ain . pl e as e s ee fig u r e x a n d t abl e x for det a ils. v dd v r r h v r r l t s r t p o r h t i m e fi g ure 7. por t iming dia gr am s t a t e / m ode res p ons e t im e to curr e nt in s t ate / m ode tx rx s hu t d o wn s t a te 15 m s 15 m s 3 0 na s t andby s t ate sl e e p s t ate s p i a c tive s t ate r e a d y s t a t e tx t u ne s t ate r x t une s t ate 4 4 0 s 4 4 0 s 3 4 0 s 1 2 6 s 5 8 s ? 4 40 s 4 40 s 3 40 s 1 22 s ? 7 4 s 5 0 na 9 00 na 1 . 35 m a 1. 8 ma 8 m a 7.2 m a tx s t ate ? 138 s 18 m a @ +10 dbm r x s t a t e 1 3 0 s 7 5 s 1 0 or 1 3 ma * n o te : t x ? rx and rx ? tx s t ate tra n sit i on timing can be r e duced to 70 s if u sing z e ro - if mode.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 10 t able 1 0 . por t iming v a ria b le des c ripti o n min t yp max uni t s t p o rh h igh time for vdd to fully se t tle p o r c ircuit 10 ms t p o rl lo w t i m e fo r vd d t o e n abl e por 10 ms v r r h v o l t age for success f ul por 9 0 %*vdd v v r r l s t arting v o l t age for success f ul por 0 1 50 m v t sr slew rate of v d d f or succes s ful p o r 1 m s 3 . 3 . 2. s hu t dow n s t a t e t he shu t d ow n s t at e i s th e l o w e s t cur r e nt co n s u mptio n s t a t e of th e d evic e wit h n o min a lly l e s s t h a n 10 0 n a o f cu r r e n t co n s u mptio n. th e s h u t d o w n s t at e m ay b e e nte r e d b y d r ivi ng th e pe/d , pi n low t h e pe/d pi n s h ou l d b e he l d high i n al l s t a t es exc e p t th e s h u t d o w n s t ate . i n th e shu t d ow n s t ate, the cont e n t s of the registe r s are lost a n d there is no spi ac c e s s. when coming out of the shu t down s t ate a power on reset (por) will be initiated along w ith the internal calibrations. a f ter the por the power_up c ommand is required to initiali z e the radio. the pe/d p i n n eeds t o be h el d low f or a t l e as t 5 0 m s b efo re d r ivin g high a g ain s o tha t i n t e r n a l ca p acit o r s ca n disc h a r ge . not h oldi ng t he pe/d low f or t h i s p e rio d of ti me m a y ca u s e th e po r t o b e misse d an d th e d e vic e t o b o ot u p inco r r e ctl y . i f po r timi ng a n d v o l t ag e r eq u ir e me n t s c a n n o t b e m e t , i t i s hi ghl y r eco m me n de d th at pe/d b e co n t r oll ed u si ng the h o st processor r a ther than tying it to vdd on the board. 3 . 3 . 3. s t a n db y s t a te s t a nd by s t ate h a s t h e l o w e st c u r r e n t c o n s u mp ti o n with t h e e xce p t ion of s hu t d o wn but h a s m uch f a st e r r e s po n s e ti m e to rx o r t x mo d e . i n mo st c a s es s t a n d by s h o u ld be used as the low power s t a t e. in this s t ate the r e gister val u e s a r e m a in t a ine d wit h al l othe r block s dis a ble d. t h e spi is accessible during this mode but any spi event, in c luding fif o r/ w , will enable an internal boot o s cillator a n d automatically mo v e the p art to spi a c tive s t ate. a f ter an spi event the host will need to r e - c ommand the de v ice b a c k to s t andby through the ?change s t ate? api com m and to achieve the 50 na cur r e n t consu m pti on. if an inte r ru pt ha s occu r r ed (i . e . , th e nir q pi n = 0) the i n t e r r u pt r e gister s m u s t b e r ea d t o a c hi ev e th e mi ni mu m cu r r e n t c o nsum p ti on o f t h i s m o de. 3 . 3 . 5. spi a c ti v e s t a te in spi acti v e s t ate the s p i and a boot up oscillator are enabled. a f ter s p i tran sactions during either s t andby or sleep the device w i l l not a u tomatically return to the s e s t ates. a ?change s t ate? api command w ill be required to r etu rn t o eithe r t he s t a n d b y or sle ep mo d es. 3 . 3 . 6. r e a d y s t a te r e a d y s t a te is d e si gn ed t o gi v e a f a st t r a n si t ion t ime t o t x o r r x s t at e wit h r eas o na b l e c u r r e nt c o nsum pt ion . i n this mode the c ry s t al oscillator remains enabled reducing the time required to swit c h to tx or rx mode by eliminating the cr y s t a l s t ar t - up time. 3 . 3 . 7. t x s t a te t he t x s t at e ma y be e nte r e d f r o m a ny o f th e s t at e wit h t he ? s t a rt tx ? o r ? c h a n g e s t ate ? api c o mm a nds . a b uilt - i n sequencer t a k es care of all the a c tions required to tran s ition between s t ates from enabling the cr y s t a l o s cillator to ramping up the p a. the follo w ing sequence of e v ent s will occur automatically w hen going from s t andby to tx s t ate. 1. enable internal l d o s . 2. s t art up cr y s t a l oscillator and wait un t il ready ( c ontrolled by an i n ternal timer). 3. enable pll. 4. c alibrate v c o/ p ll. 5. w a it until p ll set t les to r e q u ire d t r a n sm i t fre q u e nc y ( c o ntr o lle d by a n i n ter n a l time r ) . 6. activat e p o w er a m plifie r a n d wai t unti l p o w er r a mp ing is completed (controlled by an internal timer). 7. t ransmit p a c ke t .
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 11 8. rf amp began to control given voltage s t e p s i n t h i s se q ue n c e ma y b e elimi n ate d d epe n d in g on w h ic h s t ate t he chi p i s config u r ed t o p r io r t o co m ma n di ng t o tx . b y d efa ul t , th e vc o a nd pl l a re c a lib r ate d e v e ry tim e th e pl l i s e n abl e d . w h e n t he s t a r t_ tx api command is utilized the next s t ate may be defined to ensure optimal t i ming and turn around. figure 8 sho w s an example of the commands and timing for the s t a r t_tx command. cts will go high as soon as the seq u e n cer pu t s the p art into tx s t ate. as the se q ue n c er i s ste p pi ng th r o u g h t he ev en t s liste d a b ove , cts will be low and no new c ommands or property changes are all ow ed. if the fast response (fr r ) or nirq is used to monitor the current s t ate there will be slight delay caused by the internal h a rdware from when the event actually o c curs to when the transition occurs on the frr or ni r q. the ti me from entering tx s t ate to when the frr will update is 5 s and t h e t i me to when the nirq w ill transition is 13 s. if a gpio is programmed for tx s t ate or used as contr o l for a tra n smit/receive switch ( t r switch) there is no dela y . c ts n s el s d i s ta r t _ tx c u r r e nt s ta t e y yy s t a t e t x s t a t e tx c o mp l e te_s t at e f r r y y y s t a t e t x s t a t e t x c om p l e t e _ s ta t e n i rq g pi ox ? tx st a t e 3 . 3 . 8. rx s t a t e figure 8. s t art_tx comma n ds and t iming t he r x s t at e m a y be e n t e r ed fro m a n y o f t he oth er s t ate s b y u si ng th e ? s t a rt rx ? o r ?ch a ng e s t at e ? ap i c o mma n d . a b uilt - i n se q ue n c er t ake s ca re of al l t he a ctio ns r e qui r e d to transition between s t a t e s . the following sequence of e v ent s will occur automat i c ally to get the chip into rx mode when going f r om s t andby to r x s t ate: 1. ena b l e t he di gi t a l ld o a nd th e a n al og ldos. 2. s t art up cr y s t a l oscillator and wait un t il ready ( c ontrolled by an i n ternal timer). 3. enable pll. 4. c alibrate v c o 5. w ai t u nti l p ll settl es t o r e q u ire d rec e iv e f r eq u enc y (co n t r oll ed b y an int e r n al tim e r ). 6. enable receiver circui t s: lna, mixers, and adc. 7. e na ble r e c ei v e mo de in t he d igi t a l mo d em . depending on the configuration of the rad i o, all or some of the following functions will be performed automatically by th e di gi t a l m o de m: agc , af c ( o ption al), update s t atus registe r s, bit syn c h r o n ization, p a cket handling (optional) in c lu d ing sy n c w o r d , h e a de r c h e c k, a n d c r c. si m ilar t o t h e t x s t a t e, t h e n e x t s t a t e a f ter r x ma y be de fi n ed in the ? s t a rt rx? api command. the s t a r t_rx c ommands and timin g w ill be equivalent to t h e timing shown in figure 8.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 12 3.4. application pr o g ramming interface (api) an application programming interfa c e (api), which the host mcu will commu n i c ate with, is embedded in s ide the d evic e. th e ap i i s di vi d e d int o tw o s e cti o ns , comm a n ds an d p r o p e r ti e s . th e comm a n ds a re u s ed t o cont r o l t he chip and retrieve i t s s t atu s . the p r operties are general c o nfigurations w hi c h will ch ange infreque n tl y . the api d e scriptions can be found in?an625: si446x api descriptions?. 3.5. interru p t s t he trw - hp9m2w i s ca p a ble of ge n e r atin g a n inte r r u p t sign al when cer t ain even t s o c cu r . the chip notifies the m icr o c o n t r o ller t h a t an i n t e r r u p t e v e n t h a s o c c u r r e d by setti ng t he nir q outp ut pi n l o w = 0 . t hi s i n ter r u pt sign al will be generated when any one (or more) of the inter r upt e v en t s ( c orresponding to the interrupt s t atus bi t s) o c cu r . the ni r q pin will rema i n low until the m i crocontroller reads the int e rrupt s t atus r egisters. the nirq output signal will then be re s et unt i l the next change in s t atus is dete cted. t he i n t e r r u p t s so u rce s a r e gr o u p e d i n t o th r e e g r o u p s: p acke t h a ndl e r , chi p s t atus , an d mo d em . t he i n dividu al i n t e r r u p t s i n t h es e g r o u p s c an b e e n abl e d/disa b le d i n t h e inte rr up t pr o p e rt y r egiste r s , 01 0 1 , 0 1 0 2 , a n d 0 1 03 . an i n t e r r u pt m u s t b e en a ble d f o r i t t o t r ig g e r an eve nt on t h e n ir q pi n . th e i nter r u pt g r o u p m u s t b e en a bl ed a s wel l as the individual inter r u p t s in api property 0100. number command su m mary 0 x 20 g e t _ i n t _s ta t u s retu r n s th e i n t e r r u pt s t atus ? p acke t h an d le r , m o de m, a nd chip 0 x 21 get_p h_s t a tus returns the p acket handler s t atus. 0 x 22 get _ modem _ s ta t us retu r n s t he mo d e m s t atu s byt e. 0 x 23 get _ chip_s t a tus r etu r n s t he c h i p s t atus. number property default summary 0x0 1 00 int_ct l _enab le 0x 04 e n a b le s i n t e r r u pt g r o u p s f or ph , m o de m, a nd c hi p . 0x0 1 01 int_ct l _ph_enab le 0x 00 p a ck et h a nd l e r i n t e r r up t e n abl e p r o pe r t y . 0x0 1 02 int _ ctl _ modem_enable 0x 00 mo d e m inte r r u p t e n a bl e p r o p e r t y . 0x0 1 03 int _ c t l_chip _ enable 0x 04 c hip inte r r u p t e n a bl e p r o p e r t y . onc e a n inte rrup t even t occ u r s an d th e n ir q pin i s lo w t h e re a r e tw o w a y s t o r e ad an d cl e a r th e int e r r up t s . al l of the interrup t s may be read and cleared in the ?get_int_ s t a tus? api c omm a nd. by default all interrup t s will be cleared once r e a d . if only spe c ific inter r u p t s want to be read in the faste st possible method the individual inter r u p t g r o u p s ( p ac k et h andl e r , c h ip s t at u s, m o de m) ma y b e r e ad an d cl e a r e d b y t he ?get_ m odem_s t a tus?, ? g e t _p h _s ta t us? ( p a c k et h an dl e r ) , a n d ?get_chip_s t a t us? api commands. t he in s t a n t a n e o u s s t a t us o f a s pe cific f u n c t ion m ay b e r e ad if t he s p e c ific i n t e r r u p t is e n a b l e d o r d is able d . th e s t atu s r e s u l t s a re p r ovide d a f t er th e inte r r u p t s a n d ca n b e r e ad wit h th e sam e com m an ds a s t he inte r r u p t s. the s t atus bi t s w ill give the current s t ate of the function whether the inter r upt i s enabled or not. t he f a s t r e s p o n s e r e gi ste rs ca n al s o gi v e i n f o r m atio n a b ou t t he inte r r u p t g r o u p s b ut r e a d in g th e fas t r espo n se regi s ters will not clear the inter r upt and reset the nirq pin.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 13 3.6. gpio four general purpose io pins are a v ailable to utiliz e in the a p plication. the gpio are configured by the gpio_pin _ c f g co m ma nd i n a ddr es s 1 3h . f o r a c o mpl e t e lis t o f t he gpi o o p tion s pl e a s e se e th e ap i gui d e . gpi o pi n s 0 a n d 1 sho u l d b e u s ed f or activ e sig n al s s u c h as d a t a o r clock . gpi o pi ns 2 a n d 3 h a v e m o re susceptibility to generating s purious in the s ynthesi z er than pins 0 and 1. the dri v e strength of the g p ios can be a d justed with the gen_config p aram e ter i n t he gp i o _p in_cf g co mma n d . b y d e f a ul t t he d r iv e st r en g t h i s set t o mi ni mu m. t he d e faul t config u r a ti on fo r t he gpio s a nd the s t ate d u ring sdn is sho w n below in t able 1 1.the s t at e o f th e i o d u rin g s h u t d o w n i s als o sh o w n i n t abl e 1 1 . as in d ic a t e d p r e v io u sly in t a ble 6 , gpio 0 has lower d r ive s t r e n g th t h a n t h e o t h e r gp i os. ?M gpio3 ? rf front - end module mo de , ??r l ow , lO??r high ,gpio0 ? lna ?t???r high, l??r low t ab l e 1 1. gpios pin sdn s t ate por default gp i o 0 0 p or gp i o1 0 c t s gp i o 2 0 p or gp i o 3 0 p or ni r q resisti v e vdd pull - up nirq s do r esisti v e vdd pull - up sdo sdi high z s d i 4. modulation and hardw a re configuration options the trw - hp9m2w suppor t s di f f e r e n t mod u lation options and can be u s e d in v a r io u s c o n fi g u ra ti o ns to t ail o r t h e d e vice to a n y specifi c ap p lic at io n or leg a c y syste m fo r d r o p i n r epl a c e me n t . t h e m od u latio n a nd co n f i g u r atio n optio ns a re set in api propert y , mod e m_mod_type. 4.1. modem_mod_type ?? s u mm a ry : m o d u latio n t ype ?? p u r p ose: ?? t h is pro p erty se l e c t s betw e en ook, f s k, 4fsk a n d gfsk mod u latio n , mod u lation so u rc e , a n d tx direct m o de control. ?? the mo d ulator must be co n f i gured for one mo d e thr o ugh the e n t i re p acket. if portio n s of t h e p acket a l ternate betwe e n fsk and 4fsk m o des, the mo d em sh o uld be p rogrammed to 4fsk mod e . ?? property: 0 x 2000 ?? default: 0x02 ?? f ields: ?? tx_direct_mode_ t ype - default:0 0 = direct m o de ope rates i n sy n chron o us m o de, a ppl i e s to tx o n l y . 1 = direct m o de ope rates i n as ynchro n ous mode, ap p lies to tx onl y . gfsk is not supp o rte d . ?? tx_direct _ mode _ g pio[1:0] - d e fa u lt: 0 x 0 0 = tx dir e ct mode us e s g p io0 as d a t a so u r c e , ap p lie s to tx on l y . 1 = tx dir e ct mode us e s g p io1 as d a t a so u r c e , ap p lie s to tx on l y . 2 = tx dir e ct mode us e s g p io2 as d a t a so u r c e , ap p lie s to tx on l y . 3 = tx dir e ct mode us e s g p io3 as d a t a so u r c e , ap p lie s to tx on l y .
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 14 ?? mod_source[1:0] - defau l t:0x0 0 = mod u lation so u rce i s p a cke t h a ndl e r fifo 1 = mod u lation so u rce i s d i rect mode p in 2 = mod u lation so u rce i s p s e u do-ra n dom ge n erator ?? mod_typ e [2:0] - de f a ult : 0x2 0 = cw 1 = o ok 2 = 2fsk 3 = 2gfsk 4 = 4fsk 5 = 4gfsk ?? r e gis t er v i e w modem _ mod_ t y pe 7 6 5 4 3 2 1 0 tx_direct_mode_type tx_di r ect_mode_gpio[1:0] mo d _s o urc e[1:0] mod_typ e [2:0] 0 0x0 0 x 0 0 x2 4.2. modulat ion t ypes the trw - hp9m2w suppor t s five di f f e r e n t modula t ion o p tions: gaussian frequency shi f t keying (gfsk), frequency - shi f t keyin g (fsk ), fo u r - l eve l g f s k ( 4g f sk ), f o ur - l eve l f s k ( 4fsk) , a nd o n - o f f k e yin g ( ook ). mi nim um s h i f t keying ( m sk) c a n a lso be c r e a t e d b y u si n g gf sk s e t t in g s. gf sk is t he r ecom m end e d mo d ulati on ty pe a s i t p r ovid es the best performance and cle a nest modulation spectrum. the modulation type is set by the ? m od_type[2:0]? r e gisters in the ? m odem_ m od_ t ype? api propert y . a contin uo u s - wav e (cw ) ca r ri er may also be selec t ed f or rf e v al uati on p u r pos e s . t h e m o dul a ti on s o u r c e m a y a l s o b e sel e ct ed t o b e a p s eu d o - r a nd om s o urc e fo r e v al uation p u rposes. 4.3. hardware configuration options t h e re a r e d i f f e r e n t r ec e ive d em o dula t or o p ti o ns t o o p t i mize the p e r f ormance a n d mutually - exclusive o p tions for h o w th e rx/t x da t a i s tr a nsf e r r e d fr om t he h o s t mc u t o th e r f device. 4 . 3 . 1. r e c e i v e d e m o d ul a t o r op t i o n s t h e re a re multip l e dem od u lato rs i n t e gr at e d int o th e d evic e t o o ptimiz e th e p e rfo r ma nce f or di f f e r en t a p plications, modulation forma t s, a n d p a cket structures. the calculator built into wds will cho o se the optimal demodulator b a s e d on t he i n p u t cri t e r ia. 4 . 3 . 1 . 1 . syn c hro n ous demo d ul a t o r t he sync h ro n o us d e mo d ulato r's i n t e r n a l f r e q ue n c y er r o r e stim a t or acq u ir es t he f r e q ue n c y e r r or base d on a 1 01 0 1 0 p r e a mbl e st r uctu r e . t he bit cloc k r e c o ver y ci r c uit l o ck s t o th e i n c o min g d a t a st r ea m wit hin f o u r tr a nsacti o ns of a ? 1 0? or ? 01? bi t st r eam. t he synch r on o u s de m odu lato r give s o p tim al p e rfo r ma n c e f or 2 - o r 4 - leve l fs k o r gfsk modulation that has a modulation index less than 2. 4 . 3 . 1 . 2 . asy n chr o nous dem o dulator t he asy n c h r o n o u s d e mo d ul a t or s h oul d be u s ed oo k mo d ulatio n a n d f or fsk/gfsk/ 4 gfs k und e r o ne o r m o r e of the following conditions: ?? modulation index > 2 ?? no n - s t a nd a r d p r e am b l e ( n o t 1 01 0 1 0 1.. . p a tt e rn) wh en t he mo d ulati on ind ex exce e d s 2, th e asynch r on o u s d em o d ul a t o r h a s b e t t er s en siti v i t y co m p ar ed t o the sy n c h r on o u s d e mo d u l a t o r . an i n t e r n al d e gli t ch cir c uit p r o v id e s a g litc h - f r e e d a t a o u t p ut a n d a dat a c lo c k si g n a l t o sim p lif y th e inte r f a c e t o th e h ost . t here i s n o r e q u ire m ent t o p e r f o r m d e g litchi ng i n t he h os t m cu. t he a s ynchronous demodul a tor will typically be utilized for legacy s y stems and w i l l have many performance benefi t s
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 15 o v er devices used in leg a cy desig n s. u nlik e t he trw - hp9m2w sol u ti on f or no n - st a n d a r d p a cket structures, there is no r e q u i r e me nt to p e r f o r m d e gli t c h ing o n t he d a t a in t he h o s t mcu. glitch - free da t a is output from trw - hp9m2w devices, and a sa mp le clo c k f or t h e a s y n c h r o no us d a t a can a lso b e s u p pl i e d to t h e h o st m c u; s o, o v e r s a m p li n g o r bit cl o ck r ecove ry i s n ot r e qui r e d b y t he h os t mcu . th e r e a re multipl e d e t e ct or o ptio ns i n t he a sy n c h r o no us de m odu lator bloc k , which will be sele c ted bas ed upon the options entered into the w d s calculato r . the async hronous d em o dula t o r 's i n t e r n al f r e q uen c y e r r or e sti ma tor is a b le to a c q u ire t he f r e qu e n cy e r r o r b a s e d on a ny p re a mb le str u ctu r e. 4 . 3 . 2. rx / t x d a t a i n te r f a c e wi t h m c u t h e re a re tw o di f f e r e nt o ption s fo r t r a n sfe rri n g th e da t a f r o m t he r f d e vic e t o t he h o s t m cu. f i fo m o d e u s es t he spi in t erface to trans f er the dat a , w hile direct m o de transfers the dat a in real time over g pi o . 4 . 3 . 2 . 1. f i f o m o d e i n fi f o m ode, t he t r ansmi t a n d r e c e iv e d a t a i s sto r e d in integ r ated fifo register memor y . the tx f i fo is a ccesse d b y w r it i n g co m ma nd 6 6h follow ed di r ectl y by th e da t a / clk that the h o st wan t s to write into the tx fifo. t he r x fif o i s accesse d b y writin g co m ma nd 77 h f o llowe d by the n u mber of clock cycles of dat a the host wou l d like to read out of the rx fifo. the rx dat a w ill be clocked out onto the sdo pin. in tx mode, if the p a cket handler is enable d , the dat a by te s sto r e d i n f i fo m e mo ry a re ? p ackag e d ? tog e t h e r with o t h e r fi el d s a n d by t es o f info r matio n t o co n st r uc t t he fin a l t r a n s m it p ac k et s t r uc t u r e. t hes e othe r p otenti a l fi el ds include the preamble, sync wor d , heade r , crc che c ksum, e t c. the configuration of the p a cket str u cture in tx m o d e i s dete r mi n e d b y t he autom a ti c pack et ha n dle r (if e na b le d ) , i n c o nju n cti on wit h a va ri et y o f pack et ha n dler p r opert i es. if the automa tic packet handler is disabled, t h e e n ti re d esir ed p acke t st r uctu re sh o ul d be l o a d e d i n to fifo memory; no other fields (such as p reamble or sync word) will be automatically added to the b y tes s tored i n fif o m em o r y . fo r fu rt he r info r matio n on t he config u r a t i on o f t he fifo s f or a specifi c application or p a cket size, s e e " 6 . d a t a h a n d ling a n d p a ck e t h andl e r" o n p a ge 3 9 . in r x mo d e , o n ly t h e b yt e s of t he r e c e ived p a ck e t str u ctu re t h a t a r e co n si d e r e d t o b e ? dat a b ytes ? a r e st o r ed i n fi f o mem o r y . w h ic h by t es o f t he r eceiv ed p a cke t a re co n si d e r e d ? d a t a byt e s ? i s d ete r min ed b y th e auto m ati c p a ck et h a n d le r (i f e n a b led ) i n c o nj u ncti on wit h t he packet h a n d l e r c on fi g u r a t io n . i f t h e au t o ma tic p a c k et h a n d l e r is disable d , all b y tes following the sync word are co n si d e r e d d a t a byte s a n d a re st o r ed i n fi fo mem o r y . th u s , even if automatic packet h a n d lin g o p e r atio n i s n o t desired, the preamble detection threshold and sync word s till need to be progr a mmed so that the rx modem kno w s when to s t art filling dat a into t h e fifo. when t he fifo is being used in r x mode, all of the recei v ed da t a may still be observed directly (in realtime) by properly programming a gpio pin as the r xd a t a output pin; this can be quite useful during application development. w hen in fifo m o de, the chip will a utomati ca lly e x i t the tx or rx s t ate w hen either the p a cket_ s ent or p acket_rx interrupt occur s . the chip w ill r e turn to the i d le s t ate p r o gr a mmed i n th e a r gu m en t of t he ?s t a r t tx ? o r ?s t a r t rx ? ap i co m ma n d , txcomp le te_s t a te[3:0 ] or rx v alid_s t a t e[3:0]. for example, the chip may be pla c e d int o tx mo de by s e n d in g t he ?s t a r t t x ? co m ma nd and by w riting the 30h to t h e txcomplete_s t a te[3:0] argument. the chip w ill tran sm it all of the c onten t s of the fifo, and the ipksent i n terrupt will occu r . when this event oc c ur s, the chip w ill return to the ready s t ate as defined by txcomp le te_s t a te[3:0 ] = 3 0 h. 4 . 3 . 2 . 2. d i re c t m od e f or leg a c y syste ms t h a t p e rfo rm p acke t h a ndli ng withi n t he h os t mc u o r oth er b aseb a n d c h ip , i t m ay n o t be d e si r a b le t o u s e t h e f i fo . f o r t h is s c e n a r i o, a dir e ct mo de i s p r ovide d, whic h b y p a sse s the fifos ent irel y . in tx dir ect m o de, t he t x mo d ulatio n da t a i s a p plie d t o an inp u t p in o f t h e chip an d p r o c e s sed in ? r e al ti m e? ( i. e ., n o t sto r e d i n a r e gist er fo r t r a n s m issio n a t a late r ti m e ). an y o f th e gpi o s m a y b e co n fi g u r e d fo r us e a s th e tx da t a i n pu t f u nction . fu r t h e r mo r e , a n a d ditio n a l pi n m ay b e r e q ui r e d fo r a t x cloc k o u tput function if gfsk modulation is d esir ed ( o nl y t he t x da t a i n p ut pin i s r e q ui r e d fo r fsk) . t o achi e v e di r ec t m ode, th e gpi o mus t b e co nf igu r e d i n th e ?gpio_pin _ c f g ? ap i co m ma nd a s wel l a s t he ? modem _ mod_ t ype ? api p r o p e r t y . fo r gf sk, ?tx_direct_mode_type? must be set to synchronous. for 2fsk or ook, the type can be set to asynchronous or synchronous. the mod_source[1:0] s ho u ld be set to 01h for a r e all direct mode conf i guration s . in rx direct m o d e, th e r x d a t a a n d r x cloc k ca n be p r o gr a mm ed for dir e ct (rea l - time) output to gpio pins. the mic r oco n t r oll er ma y t h e n p r o c e s s th e r x d a t a witho ut usi ng t he fif o o r p a cke t h a ndl er functio ns o f t he rfic. 4.4. preamble length t he p r e am ble l e n g th r e q u ir em e n t is only r e levant if using the synchro n o u s d e mo d ulato r . i f th e asynch r on o us d em o dul a t or i s b ei ng use d, the n t h er e i s n o r e q ui r em e n t fo r a c o nve n ti o nal 1 01 0 1 0 p atte r n . t he pr e am b l e detectio n th r esh old d ete r min es t he num be r of v a lid p r eam bl e bi t s th e r adi o m u s t rec e iv e t o qua lif y a
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 16 vali d p re a mbl e. t he p r e am b l e t h r e s h ol d sho u l d b e a d just ed de p e n din g on th e n atu re o f th e a p plicatio n. the r e q uir ed p r e am b l e l e ngt h t h r e s h ol d d e pe n d s o n whe n r eceiv e m o d e i s e n t e r ed i n r e latio n t o th e s t a r t of the tr a nsmitte d p a cke t a n d th e le n gt h of t he tr a nsmi t p r e a mbl e. wit h a sho r te r t h a n rec o mme n d ed p r e a mbl e d e t e ction threshold, the probability of fa l s e detection is directly rel a ted to how long the re c ei v er operates on noise before the tr a nsmi t p r e a mbl e i s r e c e iv e d . f a ls e det e ctio n o n no i s e ma y ca u s e th e ac t u a l p acke t t o b e missed . t he p re a mble d etecti on t h r e s h ol d m ay b e a djuste d i n th e m o dem calcul a t or b y mo di f yi n g t h e ?pm d e t e cti o n t h r e s ho ld? in t he ? rx p a r am e ter s t a b ? i n t he r adi o cont r o l p a n el . f or m os t ap p lic at ion s wit h a p r e a mbl e len g t h l o ng er th an 32 bi t s, t he d e fault value of 20 is r e com m ended for the preamble d e t e ction thr e shold. a sho r ter preamble detection thr e shold may be chosen if occasional false detecti ons may be t o l e rat e d . whe n a n t e n na d i v e rsit y i s e n a ble d, a 2 0 - bit p r e am b l e d etectio n t h r e s h ol d i s r ecom m end e d. w h e n th e r e c e ive r i s synch r on o usl y e n a b le d jus t b e f o r e th e s t a rt of th e p acket , a s h o r t er p r ea m bl e d e t e ctio n th r esh old ma y be used . t a bl e 1 2 d em o nst r ate s t he r eco m me n ded p r e am b l e detectio n th r esh old a nd p r ea m bl e le n gt h fo r va ri o us m o des. t a b le 12. re c omme n ded preamble length mode afc a nt e nna d i v e rs ity pre a m b l e t y p e r e comme n ded pr e a mble l e ngth re c ommend e d pr ea mb l e d e t e c t ion thr e s hold ( g ) f sk di s a b led d i s a b l e d s t a n d a r d 4 byt e s 20 b i t s ( g ) f sk en a bl e d d i s a b l e d s t a n d a r d 5 byt e s 20 b i t s (g)fsk di s abled d i s abled n o n - s t a n d a rd 2 bytes 0 bi t s ( g ) fsk e n a b led n o n - s t a n d a rd n o t su p por t ed ( g ) fsk dis a bl ed en abl ed s t a n d a rd 7 bytes 24 bi t s ( g ) fsk e n a b led en a bl ed s t a n d a rd 8 bytes 24 bi t s 4 ( g ) f sk di s a b led d i s a b l e d s t a n d a r d 4 0 sy mb ols 16 s y m b o ls 4 ( g ) fsk en a bl ed d i s a bled s t a n d a rd 4 8 symb o ls 16 sym b ols 4 ( g ) fsk n o n - s t a n d a rd n o t su p por t ed o o k di s a b led d i s a b l e d s t a n d a r d 4 byt e s 20 b i t s ook di s abled d i s abled n o n - s t andard 2 bytes 0 bi t s o o k en a bl e d n o t s u p por t ed not e s: 1 . t h e rec o mm e nded pr e a mble le n g th a nd preamb l e d e tect i on t h re shol d s l i sted a b ove are to ach i eve 0 % per. they may be shorte n ed wh e n o ccasio n al p acket errors a re to l erab l e. 2. all recommen d ed pre a m b le le n g ths a nd de tecti o n thr e s h ol d s i n clude agc and bcr sett l ing times. 3. ?s t a n dard? pre a m b le ty p e s h oul d be set for an alter n at i ng da t a seq u ence at t h e m a x d a t a rate (?101 0 101 0?) 4. ?non - s t an d ard? preamb l e type c a n b e set for any pream b le ty p e i n clu d ing ?1 0 1010 10... 5. w h en preamb l e detection thresh o ld = 0, sync word n e eds to be 3 bytes to avo i d fa l se syncs. w hen o n ly a 2 byte sy n c word is ava i lab l e t h e sy n c w o rd d e tect i on can be exte n ded by inc l udi n g t h e last p re a mble byte into t h e rx sync word sett i ng. 5. inte r n a l func tion al b l oc k s t he followin g s e ctio ns p r o vi de a n o v e rvie w t o t he k ey int e rn al block s a n d featu r es. 5.1. rx chain the internal low - noise amplifier (lna) is d e s ig n ed to b e a wi d e - b an d l n a t h a t c a n be ma tc he d with t h r ee ex t e rn al di scr et e com p o n en t s t o cov er a n y c o mmon r ange of f r eq u e n ci es i n th e s u b - gh z ba n d . th e ln a h as ext r e m el y low n ois e t o su p p r es s th e n o is e of th e followi ng s t a ge s an d a c hi e v e o p ti m a l s e nsitivity ; s o, n o e xt e rn al g ai n o r f r o n t - e nd m o d u le s a re n e c e ssa r y . th e ln a ha s g a i n co n t r ol , whic h i s contr o lle d b y t he int e rn al a u t o mati c gai n c o ntr ol (agc)
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 17 algorithm. t he lna is followed by an i - q mixe r , filte r , p ro g r a mma bl e g a i n a mplifi er (p ga ), a nd adc . th e i - q m ixe r s d o w n c o n v e r t t he s ig n al to a n in t e rm e d ia t e f r e q u en c y . t h e p g a t h e n b oos t s th e g ai n t o b e withi n dy n amic r a n g e o f th e adc . t he ad c r ej e c t s out - of - b an d bl ock e r s and co n v e r t s t he si g na l t o t he di gi t al d om a i n w h e re filtering, d e modula t ion, and p r o c e s sing is performed. peak d e tecto r s a r e integrated at the outp u t of the lna and pga f o r u s e in t he a g c al g o r it hm . t he r x a n d t x pi n s m a y be di r e ctl y tie d exte r nal l y f or o utp ut pow e r s les s th an +1 7 dbm , se e t he dir e ct - t i e reference designs on the s ilicon labs web site for more de t a i l s . 5 . 1 . 1. rx c h a i n arc h i te c t u re it is p ossi ble to o p er a te t h e rx c h ain in d i f f e re n t architecture c o nfigur a ti o ns: fixe d - i f , z e ro - i f , sca le d - i f , a n d mo d ul a ted i f . t h ere a re t rad e - o f f s b etw e en t he a rc h it e c t ures in t e rms of s e nsitivit y , s e l e ctivit y , a n d im a ge r ej e c t io n . f ixed - i f is the def ault c o nfig u r ation a nd is r ec o mme nde d f o r m o st app lica t io n s. wi t h 35 db n ative image rejecti o n a nd au t ono m o us ima g e cali b ration to achi e ve 55 db, the f i x e d - if s o l u ti o n g i v es the b e st p e rfor m a n ce f o r m o st a pplications. fix e d - if ob t ai n s t h e best sensi t ivit y , b u t it h a s t he e f f e ct of d egr ad e d s e l e ctivity a t the im a ge fr e q u enc y . an a ut o nomo u s ima g e rejecti o n c a li b ration is i n clud e d in trw - hp9m2w d e vic e s a n d desc r ib e d in more d e t ail in " 5 .2. 3 . ima g e r e jection and calibr a ti o n" on p a ge 3 1. f or f ixed - i f a n d zer o - i f , the sensiti vity is d e gra d ed for d a t a r a tes l e ss t h an 100 kb p s o r b a n d wi d ths l e ss t h an 200 khz. t he red u c t ion in sensitivity is caused by i n c r eased flicker noise as d c is a p p roach e d. t he ben efit of z e ro - if is th a t t h ere is no image fr e que ncy; s o , th e re is n o d egr ada ti o n in t h e selecti v ity c u rve, but it has the worst sensitivit y . sc a l e d - if is a tr a de- o f f b e tween fixed - if and ze r o - i f . in t h e sca l e d - if architectu r e, the ima g e f req u e n cy is p l a c e d o r h id d en in the a dj a c e nt c h an n el wh e re it o nly slig h tly d egr a d e s the t y p ical a d j a c e nt c h a n nel selectivi t y . t he sca le d - if a p pr o ach has bet ter sensi t ivity t han ze r o - if b ut s t ill some deg ra d ation in sel e c t ivity d ue to the im a ge. in sc a le d - if mod e , t h e image f r eq u ency is dir e c t ly p r opo rti o nal t o t h e c h a nne l b a n d w i d th s e l e ct e d. f i g ure 9 d e m ons tr a tes t h e t r ade - o f f in s e nsitivity bet ween the di f f e rent architectu r e o ptions.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 18 5.2. rx modem usin g hig h - p e r f o rm a nc e adc s all o w s ch a nn el filt e ri n g , im a g e r e jecti o n , a nd d em o dul at io n t o b e p e rfo r me d i n the digi t a l domain, w hi c h allows for flexi b ility in optimi z ing the device for p a r t i c ular appli c ations. the digi t a l modem p e r f o rm s t he f o ll o wi n g f u n c t io n s: ?? c h a n nel s e l e ct i on fi l ter ?? t x mod u l a ti o n ?? rx demo d u l at i on ?? automa tic gain control (agc) ?? p r eamb l e d et e ct i on ?? i nval i d p re a m b le det ec t ion ?? r a d i o sig n al s t ren g th in d icat o r (rssi) ?? a u toma t ic fr e que ncy comp e nsat i on (afc) ?? im a ge rej e c t ion ca l ib r at i on ?? p a cket h a ndl ing i n c l u d ing ezmac ? f e atu r es ?? cyclic redundancy check (crc) t he di gi t a l cha n n el filte r a n d d em o dul a t or a re o p timize d fo r ul t r a - low - powe r c o nsum pt io n a nd a re hi g hly co n fi g u r abl e. s u p p ort ed mo d ul a ti on ty p e s a re gfsk , fsk, 4gfsk, 4 f sk, gmsk, an d ook. the channel filter ca n b e c o nfig u r ed t o su p p o r t b a ndwi d th s r a ngi ng f r o m 8 5 0 dow n t o 1. 1 k hz . a la r g e v a ri e t y of d a t a r a t es a re su p po r te d r a ngi ng fr om 1 0 0 b p s up t o 1 m b p s . t h e c o nf i gu r a b l e pr e am b l e d etect or i s use d wit h t he synch r on o us demodulator t o improve the reliability of the s y nc - word detection. preamble detection can be skipped using only syn c d e tecti o n , whic h i s a v a lua b l e f e atu re of th e asy n chr o n o u s d e mo d ul a t or w h e n ver y s h o rt p r ea m ble s a r e us ed i n p r otocols , suc h a s mb u s . t h e r e c e ive d si g na l st r e n g th indicator ( r ssi) provides a measure of the signal str e ngt h r ece i v ed o n th e t u ne d cha n n e l . t h e res o lutio n o f t he rss i i s 0. 5 db . thi s hi gh - r e solutio n rss i e na b les a c c u r a te c h a n n e l p o w er m e a s u r em e n t s f o r cl e ar c h a n n e l assessment ( c ca), car r ier sen s e (cs), and listen b e fore t alk (lbt) functionalit y . a c ompre h ensive programmable p a c ket handler including key features of s ilicon labs? e z m a c is i n t e g r a t ed to c r e a te a v a r ie t y o f c o m mun i c a t ion to p olo gi e s r a ngi ng fr om p e e r - to - p e e r netwo r k s t o m e sh net w orks . the e x tensi v e programmability of the p a c ket header allows for advan c ed p a cket filtering, w hi c h, i n turn e na b le s a mix o f br o a d c a st , g r o up , an d p oi n t - t o - p oin t c o mm u nicatio n. a wi r eles s co m mu n ic at io n cha n ne l ca n be c o r r u p t e d by n oi s e a n d in t e r f e r en ce, so i t is i m p o r t a nt to k now if the re c ei v ed da t a is free of error s . a c y clic r e dundancy check ( c rc) is used to d e tect the p r e s e n ce of erroneous bi t s in each p a cket. a crc is compu t ed and a pp e nd ed at th e e nd o f e a c h tra n smitt ed p ack et and v e r i fied by the r e ceive r to con fi rm tha t no e r r o r s h a ve o c curred. the p a cket handler and crc c an significantly reduce the load on the system microcontroller allo w ing for a sim p le r an d c h eap e r microc o ntr o lle r . t he di gi t a l m o de m includ es th e t x mo d ulato r , w h ic h c o nve r t s t he t x dat a bi t s i n t o th e c o r r esp o ndi ng st r e am o f di gi t al m od u lat i o n v a lue s t o b e sum m e d wit h t he fr a ctio n a l in p u t t o t he sig m a - d el t a mo d ul a t o r . t h i s mo d ulatio n a p p r oac h r e s u l t s i n hi g hl y accu r at e r esol u ti on of t he fr e q u enc y d e vi a ti o n . a gaussia n filt er i s im pl em e nt e d t o sup p o rt gfs k a nd 4 g fsk, con s iderably reducing the energy in adja c e n t ch a nn e ls . t h e defa u l t ba n dwi d t h - tim e p r od u c t (b t ) i s 0. 5 fo r al l pr o g r am m e d dat a r a t e s , b u t i t m ay be a djuste d to o t h e r v a lu e s. 5 . 2 . 1. a u t o m a t i c g a in c o nt r o l (a g c) t he agc a lg or i t hm is i m pl em e n t e d d igi t a lly u s ing an a d v a n c ed co n t ro l l o op o p ti m iz e d f or f a s t r e s p o n se t im e . th e agc o c curs within a single bit or in less than 2 s. peak d e t e ct o r s a t th e o u t p u t o f th e ln a a nd pg a allo w for o p timal adjustment of the lna gain a n d pga gain to optimize im3, selectivit y , and sensitivity performance. 5 . 2 . 2. auto fr e q u e ncy corre ct ion ( a f c ) frequency mistuning caused by crys t al ina c cur a cies c a n b e co m pen sate d fo r by e n a b lin g th e di gi t a l a u t o matic fr e q u enc y c o ntr ol (a fc ) i n r e c e iv e mo d e . t he re a re t w o ty p es o f i n t e g r a t ed f r e q ue n c y com p ensati o n : m o d em fr e q u enc y com p e n s a ti o n , a nd a f c b y a d justin g t he p ll f r eq u e n c y . wit h a fc disabl e d , th e m o dem com p ensation ca n c o r r ec t f or f r eq u enc y o f fs e t s up t o 0.2 5 ti m e s t he i f b an d wi d t h . whe n t h e af c i s e n a b led , th e r ece i v ed sign al will be centered in the p a ss - band of the if filte r , providing optim a l sensitivity and selecti v ity over a w ider range of fr e q u enc y o f fse t s u p t o 0. 35 tim es th e i f ba n dwi d t h. whe n a fc i s e na b led , t he p r ea m bl e le n gt h n e ed s t o be lo ng e no u g h t o s e ttl e th e afc . a s sh o w n i n t a ble 1 2 o n p a ge 28 , an additional byte of preamble is typically r e q u ired to settle the afc.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 19 5 . 2 . 3. im a ge r e je ct ion and c a l i br a t i o n sin c e the re c ei v er utilizes a low - if ar c hitecture, the selectivity w i ll be a f fected by the image frequenc y . the if frequency is 468.75 k hz (fx t al/64), a n d the image frequency will be at 937.5 k h z below the r f frequenc y . the n ativ e i m age r ejectio n o f t he trw - hp9m2w famil y i s 3 5 db . i m age rejection calibr a tion is a v a il a ble in t he trw - hp9m2w to im p r o v e t he ima ge r e jecti on t o m o re t h a n 5 5 db . t he c a lib r atio n i s initiate d wit h t he irca l ap i comm a n d. t he cali b r a ti on u s es a n inte r n al sign al sou r ce , s o no ex t e rn al sig n a l g en e r a t or i s re q ui r e d. th e initia l c a lib r atio n t akes 2 5 0 ms , a nd p e ri o di c r e - cali b r a ti on t a k es 10 0 m s . re - c a lib r atio n s h o u l d b e initiate d whe n th e te m per atu re h a s ch a ng ed m o r e th an 3 0 c. 5 . 2 . 4. r e c e i ve d si gn al s t r e ngth indicator t he r e c ei v ed s ig na l s t r e n g th in d ic a t o r (r s si) is an e s ti m a t e of t he s ig n al s t r e n g th in t h e c h a nn el to w h ich th e r eceive r i s t u n e d . t h e rss i me a s u r e me nt i s d on e a f t er the channel filte r , so it is o n ly a measu r ement of the d esir ed o r u nd e si r e d i n - b and si g na l p o w e r . th e r e a r e tw o di f f e r e n t m eth o d s fo r r e a di ng t he rss i v a lu e a nd s e ver al di f f e r e nt o ption s fo r co nf igu r i n g t he rss i v a lu e th at i s r e tur n e d. t he fast e s t m e t h o d fo r r e adi ng th e rss i i s to co n fi g u re o n e o f t he fo ur f a s t r esp o ns e r egiste rs (frr ) t o r e t u r n a l a tc h e d rss i val ue. th e l a t c h e d r ssi v a lue is m e asu r e d o nc e p er p acke t a n d i s latche d a t a c o nfig u ra b l e a m ount of tim e a f t er r x m ode i s e n ter e d . th e fast r e s p o n se r e gi s t e rs c an be r e ad in 1 6 sp i cl o c k cycl es wit h n o r e qui r em e n t t o wa i t fo r cts . t he rss i v a lu e may al s o b e r e a d o u t o f th e get_ m odem_s t a tu s comm a n d. i n t h i s co m ma n d , b o t h t he cu r r e n t rss i a n d th e l atched rssi a r e available. the cur r e n t rssi value represen t s t he sig n a l st r e n gt h at the ins t ant in time the get_mode m _s t a tu s co m ma nd i s p r o c e sse d an d ma y b e r e ad multiple tim e s per p acke t . reading the rssi i n th e get_ m odem_s t a tu s c o mma n d t a k es l o ng er th an r e a d in g the rssi out of t he fast response registe r . a f ter the i n itial command, it w ill t a k e 33 s f or ct s t o b e se t a nd the n t he f o u r o r fiv e byte s o f sp i cloc k cycl es t o r ead o u t t h e r e s p ec t ive c u r r e n t or l a tc h ed r ssi val ue s. t he rss i config u r a ti on o p ti o n s a r e s et i n th e mode m _rssi _ con t ro l ap i p r o p e r t y . th e l a tc h e d rss i value m ay b e latche d a nd sto r e d b a s ed on th e followi ng e v e n t s: p r ea m bl e d e t e ctio n, sy nc d e tection, or a con f igurable n um b e r o f b it t im e s me a s u r ed a f t er t h e s t a r t o f rx mo de ( minim um o f 4 bi t ti m es) . t he r e q u ire m en t fo r f o u r bit tim es i s d e t e r m ine d by th e p r ocessin g d e la y a n d set t l i n g t h r o u gh t he m od em and di gi t a l cha n n el filte r . in modem _ rssi_ c ontrol, the rssi may be d e fined to upda t e e v e r y bi t p eri od o r t o b e a v e r a ged a n d u p dated e v ery four bit periods. if rssi avera g ing over four bi t s is enabled, the latched rssi value will be delay ed to a minimum of 7 bi t s a f ter the s t a r t of rx mo de to all o w f o r t he a v e r a g i n g. th e latched rssi values are cleared when e nte ri n g r x m o d e s o th ey m ay b e r ead af t er th e p a ck et i s r eceive d o r a f te r d r o p pin g b ac k t o s t a nd by m o de . i f t he rssi value has been c l eared by th e s t ar t o f r x bu t n o t latched y et, a v alue of 0 will be returned if it is attempted to be r e ad. t he rss i v a lu e r e ad b y t he ap i c o ul d be t r a n sl at e d t o db m b y t he followi ng line ar e q uati o n: rss i (in dbm ) = (rssi_valu e / 2) ? rssical rssic al i n t he a bov e f o r m ul a de p e n d s o n th e matchin g n etw o rk , m o de m setti n gs , a nd e xte r n al ln a g ai n (if p r e s e n t ) . t h e rs s ic a l v al u e c a n be obt ai ne d by a si mp le cali b r a ti on wit h a sign al g en e r a t or con n ecte d a t t he a n t en na i n p u t. wit hout e xt e r n al l n a, t he v al u e of rss i c a l is a r o u nd 13 0 3 0. during p a cket r e cep t ion, it may be useful to d e tect w h e t h e r a seco n da ry i n t e rfe r in g sig n a l (d es ire d or u n desi r ed) a r ri v e s . t o d e tec t thi s eve n t , a fe at ur e f or rss i j u m p d e tection is available. if the r ssi level changes by a p r o gr a mma bl e a mo u n t dur in g t he r e c e ptio n of a p a cket , a n i n t e r r u pt or g pio c a n be c o n f ig ur ed to n o t ify t he h o s t. t he l e v e l of rs s i i n c r e a se or decr ease ( ju mp ) is pr o g r am m abl e th r ou gh t he m odem_rssi_ju m p _ thres h api p r o per t y . i f a n rss i ju mp i s d e t e ct e d , t he m odem m ay b e p r o g r amm ed to a u t o m a ti c ally reset so t hat it may lock o n to the n e w st ro n g er s ig na l. th e c h ip ma y also be c o nfigu r e d t o auto m atic a lly r ese t th e r e ceive r u p o n jump d e tection in o r d e r to acquire the n e w signal. the con f iguration a n d o p tions for rssi jump dete c tion are p r o gr a mmed i n t he modem _ rssi_cont r ol2 api p r opert y . by d e fault, rssi jump detection is n o t enabled.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 20 t he rss i v a lu es a nd c u rve s may b e o f fs et by th e m o dem _ rssi_com p api p r o pe r t y . t he defa u l t val ue o f 7? h32 c o r r e s p o n d s to no r ssi o f f s e t. se t ti n g a v al u e le s s t h a n 7? h3 2 c o r r espo n d s t o a n e g ativ e o f fset , a n d a val ue hi g her th an 7?h 32 c o r r esp o nd s t o a p ositiv e o f fset. the o f fset value is in 1 db ste p s. fo r e x a mp le, s e t t i n g a v al u e of 7 ?h 3 a c o r r e s p o n d s to a p o si t ive o f fs e t of 8 db. cle ar c h a n ne l as sess m ent (c ca ) or rss i th r esh old d etect ion is also available. an rssi thr e shold m a y be set in the modem_rssi_thresh api propert y . if the rssi value is a bov e t h i s t h res h old , an inte rrup t o r gpi o may n otif y t he h o st . b o t h th e l atc h e d ve r si on a nd asy n chr o n o u s version of this thr e shold are available on any of the gpios. automatic fast hopping based on rssi is avail a bl e . se e ? 5 .3.1.2 . a u t o mati c r x hop p in g a n d ho p t a bl e ?. 5.3. synthesizer synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. the transmit modulation is applied directly to the loop in the digital domain through the fractional divider, which results in very precise accuracy and control over the transmit deviation. the frequ ency resolution in the 922 ? 928 mhz band is 28.6 hz with more resolution in the other bands. the nominal reference frequency to the pll is 30 mhz, but any xtal frequency from 25 to 32 mhz may be used. the modem configuration calculator in wds will automatic ally account for the xtal frequency being used. the pll utilizes a differential lc vco with integrated on - chip inductors. the output of the vco is followed by a configurable divider, which will divide the signal down to the desired output frequency band. 5 . 3 . 1 . sy n t h e sizer fr e que n cy control the frequen c y is set by c ha n ging the integer and fractional s ettings to the s y nthesize r . the w d s c al c ulator will a utom a ticall y p r ovid e t h es e s e tti n gs , b ut t he synth e siz er eq u atio n i s sh o w n b e lo w fo r co nv eni e nce . t h e api s for setting the frequency are freq_ c on t r ol_inte, f re q _c o n t r ol _ f ra c 2, f re q _ c o n t r o l _ f r a c1, an d freq _c ontrol _ frac 0. 5 . 3 . 1 . 1 . ez fre q ue n cy prog r amming in applications that u t ilize mult i p le frequencies or ch a nnels, it may not be desirable to write four api regi sters eac h tim e a f r equ enc y c h an ge i s r e q ui r ed . e z f r e q ue n c y p r ogr a m min g i s p r ovid ed s o t h a t o nl y a si n gl e r eg i ste r w r ite ( c h a n ne l n u mb e r ) i s r e q uir ed t o ch a ng e fr e q u enc y . a ba se frequency is first set by first programming the integer and fract i onal compon e n t s of the s ynthesi z e r . this ba s e frequency will correspond to channel 0. ne x t, a channel ste p siz e i s p r o g r a mme d int o t he f r e q _ c o n t r ol_ c han n el _step_size_ 1 and freq_control_c h ann e l_step_ s ize_0 a p i reg i sters. the resulting frequency w ill be: rf frequ e ncy = base frequ e ncy + c h anne l ? steps ize t he s e c o nd a r g u me nt of t h e s t a r t_ rx o r s t a r t _ t x is cha n nel, which se t s t h e c h a n n e l n u mb er f o r ez f r e q u ency p r o g r amm in g . fo r ex am pl e , if t he c h a n ne l s t ep si z e is s e t to 1 m hz, t h e b a se f r e q ue ncy is s e t t o 9 0 0 m hz with the inte and frac api registers, a n d a channe l n um b e r o f 5 i s p r og r am m e d d u ri ng t he s t a r t_tx command, the re s u lting frequen c y will be 905 m hz. if no chan n el argument is written as p art of the s t a r t_r x /tx command, it will default to the previous value. the initial value of c han n el is 0; so, if no cha n nel value is written, it will re s u lt in the programmed bas e frequenc y . 5 . 3 . 1 . 2 . aut o m a tic rx ho p p ing and hop t a ble t he t r ansceive r su p po r t s a n a u t o mati c h o p p in g f e atu re t h at c an be f u ll y c o nfigu r e d th r ou gh th e api . thi s is i n t e nd ed f or r x h o p pin g whe re t he d evic e h a s t o hop fr om ch a nnel t o c h an n e l a n d lo ok f or p a ck e t s . onc e the d e vi c e is p ut i n to t h e rx s t a t e, it automatically s t ar t s h o p p ing thr o ugh t h e h o p t a bl e i f th e f e atu re i s e n a b led. t he h op t a bl e ca n hol d u p t o 64 e n t r ie s a nd i s mai n t ain ed i n fi r mwa r e . e a c h e n t ry i s a ch a n n e l n u mb e r ; s o, th e h op t a bl e ca n h o l d up t o 64 ch a n n els . th e n um b e r o f ent r i es in the t a ble is set by r x hop t a b le_size api. the sp e cifi ed ch a nn e l s cor r esp o n d t o th e e z f r eq u e n c y p r o g r ammi ng m eth od fo r p ro g r a mmi ng th e fr e qu e nc y . t he receiver s t ar t s at the bas e channel and ho p s in sequence from the top of t h e hop t able to the bottom. the t able will wr ap ar o u nd t o t he bas e cha n ne l o n c e i t r each es th e en d of t he t a bl e. a n e ntr y of 0xf f i n th e t a bl e ind i c a t es t h at the entry s hould be skipped. the devi c e will hop to the next non 0 x ff entr y . t h e re a r e t h r ee c o n d iti o ns t h at c an be u s ed to d e t e r m i n e w h e t h e r t o c on ti n ue h op pi n g o r to s t a y o n a p a r tic u l a r ch a n n e l . t h es e con d ition s a r e: ?? rssi threshold ?? preamble timeout (in v alid preamble p a tter n ) ?? syn c w o r d tim e o ut (i nv ali d o r n o syn c wo rd d e t e ct ed a f te r p r e am b le)
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 21 t h es e con d ition s c an b e u s ed in di vi d u a lly , o r t h e y c an b e e n a b le d al l to g ethe r b y c o nfigu r in g th e rx_hop_ c o n t r ol a p i. howeve r , the fir m ware will make a decision on whether or not to hop based on the first c o n d iti o n t h at is m e t. t he rss i t h a t i s mo ni t o r ed i s th e cu r re nt rss i valu e. t his is c o m p a r ed to t h e t h r e s h old, and, if it is above the threshold v alue, i t will s t ay on the c hannel. if the r ssi is below the thre s hold, it w i l l continue hopping. there is no a v e r a g i n g o f rssi d o ne d ur ing t h e a u t o ma tic h o pp i n g fr o m c h a n n e l to c h a n n e l. si n ce t h e p r e a mb le ti me o u t a nd th e syn c w o r d tim e o ut a re fe a t u r es th at r eq u ir e p acke t ha nd li n g , t he rss i t h r e s h ol d i s the only con d ition that can be used if the user is in ?dire c t? or ? r a w? m ode wh e r e p a cke t ha n dli ng f e atu r e s ar e no t use d. note that the rssi threshold is n o t an absolute rssi value; instead, it is a r e lative value and sho u ld be verified on t h e b ench to fi n d an op ti m al th re sh o ld f o r t h e a p pli c a t io n . t he t u r n ar o u nd tim e fr om r x t o r x o n a di f f e r en t ch a n n e l us in g t h i s m e t h o d i s 1 1 5 s . t he tim e spe nt i n r e c e ive mode will be determined by the c onfi g uration of the hop conditions. manual rx hopping will have the fa s test turn - around time but will require more overhead and management by the host m c u. t he followin g ar e exam ple st e p s f or usin g a u t o h o p: 1. set the b a se frequency (inte + frac) and channel step size. 2. d e fi ne th e n u mb er o f e n t r ie s i n t he h op t abl e (rx_hop_ t able_size ). 3. w r it e t he cha n nel s t o t he h op t abl e (r x_hop_ t able_ent r y_ n) 4. c o n fi g u r e t h e h o p c o n d iti o n a n d e n a ble au to h op pi ng - r ssi, p r e am bl e , or s y nc ( r x_ h op _ c o n t r o l ) . 5. s e t p r e am ble an d s y n c p a r a me te rs i f en a bl e d . 6. pro g r am t he rss i t h r e s h ol d p r o pe r t y i n th e m o d em us in g ? modem_rssi_thresh ?. 7. s e t t h e p r e am ble t hr es ho ld u s ing ? prea m b l e_ c o n f i g _ s t d _ 1 ? . 8. pro g r am t he p r eam bl e tim e out p r ope rt y u si ng ?preamble _ con f ig_std_ 2 ?. 9. set the sync detection p a r a m e t e rs if e na bl e d. 1 0 . i f n e e d ed , us e ?gpio_pin_cfg ? t o co n fi g u re a gpi o t o t o gg l e o n h op a nd ho p t abl e w r ap. 1 1 . use the ?s t a r t _ r x? api with cha n n e l number set to t h e first v alid entry in the hop t able (i.e., the first non 0 xf f e n t r y). 1 2 . devic e s h oul d now b e i n a ut o h op mo d e . 5 . 3 . 1 . 3. ma n ual rx hopping t he rx _h o p co m ma nd p r ovide s t he f a st e s t meth od f or h o ppi ng f r o m r x t o r x b u t i t r e qui r e s mo re ove r head and management by the h o st mcu. using the rx_ho p c o mm a nd, t he tur n - a r o un d t i m e i s 7 5 s . t he timin g i s f a ster with t his m e t ho d t h a n s t a rt _ rx or rx h o p p i n g b e c a u s e on e of t h e cal c ul a ti o ns r eq ui r ed f or t h e sy n t h e s iz e r cali b r a ti o n s i s o f fl o ad ed t o th e h o s t an d m u s t b e calcu l a t e d/sto r e d by t he host , vco_cnt0 . fo r i n f o rm a ti on ab o ut u si ng f a s t m a nu al h o p pin g, co n t ac t custom er s u p p o r t. 5.4. t r a n smitter (tx) t he trw - hp9m2w con t ain s an inte g rat ed + 20 db m t r a n sm i tte r or power amplifier that is ca p able of transmitting from ? 2 0 t o +2 0 d bm . th e o utp ut p owe r ste p s a re les s t h a n 0 . 25 d b wit hin 6 db of m a x powe r b ut b e com e la r ge r and m o r e n on - lin e a r clos e t o mini m u m o u t p u t p owe r . t he si44 6 4/6 3 p a i s d e sign ed t o p r o vi de t he hig h es t e f ficiency a n d l o w e s t cur r e nt co n s u mpti on possibl e. t he si4 4 6 1 p a i s c a p a bl e of t r ansmittin g fr om ? 40 t o + 16 dbm . the si 4 46 1 p a ca n be o ptimi ze d f or ei t h e r optim um cu r re nt c o nsum p ti on ( clas s e ) o r fo r fi ne o u tpu t p o we r ste p s and performance o v er vol t age and temperature ( s wit c hed - current). switched - c urr e nt mat c hing w ill have fine output power s te p s and more cons t ant output pow er o v er vdd, but it will ha v e higher c u rrent c onsumption than the class - e matching. the class e will have t h e most e f ficient current consumption, but it will h a ve more c oar s e output p owe r ste p s a nd v a ri a ti on acr o s s vdd . t he si 4 4 60 i s d e si g ne d t o sup p l y +1 0 d b m o utpu t pow er f or les s than 20 m a fo r ap p lication s th at r e q ui re o pe r atio n f r o m a sin g l e coi n cel l b a tt e r y . t he si4 4 6 0 c an al s o o p er ate with ei t h e r class - e o r switch ed cu rren t m a tc hi n g an d o u t p u t up t o + 13 db m tx powe r . al l p a optio ns a re sin g le - end e d to a llo w f or e a s y a n ten na m a tchi ng a nd lo w bo m c o st . a u t o mati c r a mp - u p a n d r a m p - dow n i s a u t o matically p e r f o rm ed t o re d uc e u n w a nte d sp ec t r a l spr e a d ing. chip ? s t x ramp pin is disabled by default to save c u rrent in cases where on- chip p a will be able to drive the antenna. in ca s e s where on- c hip p a w ill drive the e x ternal p a , and the external p a needs a ramping signal,
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 22 txramp is the signal to u s e. t o enable txram p , s e t the api property p a _mode[7] = 1 . txramp will s t art to r am p u p , an d r a mp dow n at th e sam e ti me a s t he inte r na l o n - c hi p p a r am p s up/d o wn. t he r a mpi ng spe ed i s p r o g r amm ed b y tc[ 3 : 0] i n th e p a _ramp_e x ap i p r o p ert y , w h ic h has t he following chara c teris t ics: tc ramp t i me (s) 0.0 2 .0 1.0 2 .1 2.0 2 .2 3.0 2 .4 4.0 2 .6 5.0 2 .8 6.0 3 .1 7.0 3 .4 8.0 3 .7 9.0 4 .1 1 0 .0 4 .5 1 1 .0 5 .0 1 2 .0 6 .0 1 3 .0 8 .0 14.0 10.0 15.0 20.0 t he r a m pin g p r ofil e i s cl ose t o a lin ea r r am p in g p r ofil e wit h sm o oth ed o u t co r ner wh en a ppr o a c h in g vh i a n d vlo. the tx r amp pin c an source up to 1 ma without vol t age drooping. the txramp pin ? s sinking c a p ability is equivalent to a 10 k ? p u ll- down r e sis t o r . vhi = 3 v w hen vdd > 3.3 v . when vdd < 3.3 v , the vhi will be c losely following the v d d, and ramping time will be smaller al s o. vlo = 0 v w hen n o current needed to be sunk into txramp pin. if 10ua need to be sunk into the chip, vlo wi ll be 10 a x 10 k = 1 0 0 m v . number command summary 0x2200 p a_mode se t s p a type. 0x22 01 p a_pwr _ l vl a dj u s t t x pow er i n fin e st e p s. 0x2202 p a_bias_clkduty adju s t tx power in coarse s te p s a nd o p ti mi z es fo r di f f e r e n t m a t ch c o n f ig u r a ti o n s . 0x22 03 p a_ tc ch a ng es t he r am p up/d o w n time of the p a.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 23 tx power(dbm) 5 . 4 . 1. trw - hp9m2w :+20 d bm p a the + 20 d bm c onfiguration utili z es a c la s s - e matching c o nfiguration. t ypi c al perfor manc e fo r th e 900 m hz band fo r o utpu t p owe r ste p s , v o l t ag e, a nd te m per atu re a re sh o w n i n fi g u r e s 1 0 ? 1 2 . t he o utp ut pow er i s c h ang e d i n 128 st e p s th ro u g h p a _ pw r _ l v l ap i . f or d e t a iled m at c hi n g val ues , bom , a nd p erf o rm a nc e at o t h e r f r e q ue n cies , r efer to the p a matching application n o te. 25 20 15 10 5 0 - 5 - 10 - 15 - 20 - 25 - 30 - 35 tx p ower vs. p a_p wr_ l vl 0 10 20 30 40 50 60 70 80 90 100 110 120 pa_pwr_lvl figure 10. +20 dbm tx pow e r v s. p a_pwr_ l vl
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 24 tx p o wer ( db m ) fi g ure 1 1. + 2 0 dbm tx power vs. vdd 20.5 tx p ower vs t e mp 20 19.5 19 18.5 18 - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 te m perat u re (c) f igure 12. + 20 dbm tx power vs. t e m p 5 . 4 . 2. si 44 61 + 1 6 d bm p a the s i 4461 p a can utilize di f f erent mat c hes to optimize the performance for 16, 14, 13 d b m, or a lower powe r . a class - e m a tc h i s r e c o mme nd ed fo r 16 db m t o m a x i mi z e t h e e f ficie n cy and b a tte r y life. for 13 and 14 dbm, a swi t c h ed c u r r e n t ma tch is r e c o mme n d ed to p r o vi d e op t im al pe r fo r ma n c e ove r vd d a nd tem p er a t u r e v a ri a ti o n. t y pi c al p e rfo r ma n c e fo r t he 9 0 0 mh z b a n d fo r o u t p u t p o w er ste p s , v o l t ag e, a n d t e mp e r a t u r e a re sh o w n i n fi g u r e s 13 a n d 14 . t h e outp ut pow er i s ch a n g e d i n 1 2 8 ste p s th r ou gh t he p a_p wr_ l v l api . f or d e t a ile d matchi ng val u es , bo m, a nd p e rfo r ma nce a t o t h e r f r eq u e n ci e s , r e f er t o ?an6 2 7 : si 4 46 0 / 61 l o w - powe r p a m atc hi ng. figure 13. +13 d bm tx pow e r v s. p a_pwr_ l vl
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 25 figure 1 4 . +13 d bm tx power v s . supply v ol t a g e (vdd) 5.5. crys t al oscillator the trw - hp9m2w includes an integrated cr y s t al os c illator with a fast s t art - up time of less than 250 s . the des ign is di f f e r e n ti al wit h th e r e q ui r e d crys t a l lo ad c a p aci t anc e i n t e g r ate d o n - c hip t o minim i z e th e nu m be r o f e xt e rn al co m pon en t s . b y d e f a ult , a l l t h a t i s r eq u ir ed o f f - chi p i s t he crys t al. the defau l t crys t al is 30 mh z , but the cir c uit is d esign ed t o h a ndl e a n y x t a l fr om 2 5 t o 3 2 mhz . i f a cr ys t al di f f e r e n t than 30 mhz is used, the power_up api boot command m u st be modified. the wds calcula t or crys t al frequency field must also be changed to r e flect the fr e q u enc y b e in g used . t he crys t a l l o a d c a p aci t anc e c an be di gi t all y p r o g r a mmed t o a cco m mo d at e crys t al s with various load ca p a ci t a n c e requiremen t s and to adj u st the frequency of the cr y s t a l oscillato r . the tun i ng of the cry s t al l o a d ca p aci t a nce i s p r o gr a mmed th r ou gh th e g l obal _x o_ t un e ap i p r o p e r t y . t he t o t a l inte r n al c a p a ci t anc e is 1 1 p f an d i s a d jus t a b l e i n 12 7 st e p s ( 7 0 f f/st e p ). t h e c r ys t al f r e q ue n c y a dj u stm e n t c an be u s ed t o c o mp e nsat e for crys t al production tolerances. the frequency o f fset c h a r a cte ri stic s of t he c a p a cit or ba nk a re de m onstr a t ed i n fi g u re 1 5. f i gure 15. ca p aci tor bank fr e quency offs e t c h aracteristi cs
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 26 utili z ing the on- chip temperature sen s or and sui t able control s o f t ware, the temperature dep enden c y of the cry s t al c a n be c anc e le d . a t c x o or e xt er n a l s ig n al s o u r ce c an easil y be use d i n pl a c e of a c o nve n ti o n al x t a l a n d sho u l d b e con n ecte d to the xin pin. the i n coming clock signal is r e commended t o h av e a p e ak - to - p e a k sw i n g i n th e r a n ge of 600 mv to 1 . 4 v a n d a c - c ou pl e d to t he xin pi n . i f t h e p e a k - t o - p ea k swin g of th e tcx o exce e d s 1. 4 v pe a k - to - pe a k , the n dc c o u p li n g t o t h e xin pin s ho uld b e u s e d . th e m axi mu m a l lowe d swin g o n xi n i s 1. 8 v pe a k - to - pe a k. t he x o ca p acit or ba nk s h o u l d b e se t t o 0 whe n eve r a n e x te r nal d r iv e i s use d o n t he xi n pi n. i n a d ditio n, t he po w er_up c ommand should be in v oked with the tcx o optio n w h ene v er exte r na l d riv e i s u s e d . 6. da t a handling and packet handler 6.1. rx and tx fifos t w o 6 4 - b yte f i f os ar e i n t e g r a t ed in t o t he c h ip, o n e f or rx and one for tx, as shown in fig u re 16. w r iting to co m ma nd r e giste r 6 6 h l o a ds d a t a int o th e t x fi f o , an d re a di ng f r o m c o mma nd registe r 77 h re a d s d a t a f r o m the rx fifo. t he t x fifo h a s a threshold for when the fifo is almost empt y , which is s et by the ?tx_fifo_empty? p r o per t y . an i n t e r r u p t e v e n t o c cu r s w h en t he d a t a in t he t x f if o r e a c h e s t he alm o s t em p t y t h res h old . i f mo re da t a is not loaded into the fifo, the chip a u t o maticall y exi t s th e t x s t ate a f te r th e p a cket_sen t inte r r u p t o ccu rs. t he r x fif o h as o n e p r o g ra m ma b l e th r esh ol d , whic h i s p r o g r amm ed by s e tti ng th e ?rx_ f i f o_ f u l l ? p r op e rt y . when the in c oming rx dat a c rosses the almost full thre s hold, an int e rrupt will be generated to the microcontroller v ia the ni r q pin. the micro c ontroller w ill then need to read the da t a from the rx fifo. the r x almo s t full threshold indication implies that the host can read at l e ast the thre shol d nu m ber o f byte s f r o m th e rx fifo at that tim e . both the tx and rx fifos may be cleared or reset with the ? f ifo_reset? command.
www.wenshing.com.tw ; www.rf.net.tw trw - hp9m2w datasheet p. 27 h e a d e r o r d a ta d a ta d a ta d a ta 6.2. packet handler when using the fifos, a u tomatic p acket handling m a y be en a ble d fo r tx m o de, r x mo d e , or both . th e usu al fi e lds f o r n e t wo r k c o mm u n ic a ti o n, s u ch as p r e am bl e , s y n c h r o n iz a ti o n w o r d, h ea d e r s , p a ck e t l eng t h, a n d c rc, c a n be c o nfig u r ed t o b e a utom a ticall y a d de d t o t he da t a pa yl o a d. t he fi el d s n e ed ed fo r p acke t gen e r atio n n o r mally ch a ng e infr e q u e ntl y a n d ca n th e r e f o r e be sto r e d i n r e gi s te r s. automatically a d ding these fields to the dat a p a yload i n tx m ode a nd a u t o maticall y c h eckin g th em i n r x m o de g r eatl y r e duc es th e a mo u n t o f c o mm u nicatio n between th e mi c r oco n t r oll er a nd trw - hp9m2w . i t als o g r e a tl y r e duce s th e r e q u ir ed c o mp u t ati on a l powe r o f th e mi c r oco n troll e r . the g en e r al p a ck e t st r u c tu r e is sh o wn in f i g u r e 1 7 . any o r all of t h e fi e lds c a n b e e n a b l e d a n d c h e c k e d by t h e i n te rn al p a ck e t h a n d l e r . p r eam b l e s y n c w o r d f i e l d 1 c r c f i e l d 1 ( o p t ) f i e l d 2 ( o p t ) p k t l e n g t h o r d a ta c r c f i e l d 2 ( o p t ) f i e l d 3 (o p t) c r c f i e l d 3 ( o p t ) f i e l d 4 (o p t) c r c f i e l d 4 ( o p t ) f i e l d 5 (o p t) c r c f i e l d 5 ( o p t ) 1 - 2 5 5 b y t e s 1 - 4 b y t es c o n f i g c o n f i g c o n f i g c o n f i g c o n f i g 0 , 2 , o r 4 b y t e s 0 , 2 , o r 4 b y t e s 0 , 2 , o r 4 b y t e s 0 , 2 , o r 4 b y t e s 0 , 2 , o r 4 b y t e s f i gure 17. pa c ket handl e r s tru c ture t he fiel ds a r e hig h l y pr o g r am m abl e a nd ca n be u s ed t o che c k any kind of p a ttern in a p a c ket stru c ture. the general functio n s of the p a cket handler include the following: ?? detection / validation of preamble quality in rx mode (preamble_ v alid signal) ?? dete c tion of sync w ord in rx mode (sync_ok signal) ?? dete c tion of valid p a cke t s in rx mode (p k t _ v alid s ignal) ?? dete c tion of crc errors in rx mode (c r c_err signal) ?? da t a de - wh iteni ng a n d/o r m anch e st er d e c o din g (i f e n a ble d) i n r x m ode ?? m atc h /h e ad er checkin g i n r x mo de ?? s torage of da t a field b y tes into fifo m e mory in rx mode ?? co ns t r uctio n o f pr e am b l e fi eld i n t x mo de ?? co ns t r uctio n o f sy nc fiel d i n tx m o de ?? co ns t r uctio n o f da t a fi eld f r o m fif o m em o r y i n t x mo de ?? co ns t r uctio n o f cr c fi eld (i f e n abl e d ) i n tx m o de ?? da t a w h it e ni ng and / or m a nch e ste r enco d in g (if e na b led ) i n t x mo de f or d e t ail s o n h ow t o confi g ur e t he p a ck et h a nd l e r , se e ?a n 6 26 : pack et ha n dl er o p er a t i o n fo r trw - hp 9m2w r f ics?. 7. rx modem configuration t he trw - hp9m2w ca n e a sil y be co n fi g u r e d f or di f f e re nt da t a r ate , devia t ion, frequenc y , etc. by using the wds settings calculato r , which generates an initiali z ation file for use by the h o st mcu.
http : //w ww.wenshing.com.tw ; http://www.rf.net.tw trw - hp9m2w datasheet p. 28 wut_r -------------- 8. auxiliary blocks 8.1. w ake- up t i mer and 32 khz clock source t he c h i p co n t ai ns a n integ r ate d wake - u p time r th at c an be u s ed t o p e r io d ic a lly w a ke t he chip f r om sl e ep mo d e . t he wake - up timer runs from either t h e internal 32 khz rc o s cillato r , or from an e x ternal 32 k h z x t al. t he w a k e - up tim er c an be co n fi g u r e d t o r u n whe n i n sl e e p m o de. i f wu t _e n = 1 i n th e g l obal _ w ut _ config propert y , prior to entering sleep mode, the wake - up timer will c ount for a time s pecified defined by the global_w u t_r and glob a l_wut_m properties. at the expiration of this period, an interrupt will be generated on the nirq pin if this i n terrupt is enabled in the i n t_ctl_ c hip_ena b le propert y . the mi c rocontrol l e r will then n ee d t o ve ri f y th e int e r r up t b y re a di ng t he chi p inte rr up t s t a t us ei t h e r vi a ge t _in t _ s t a tu s or a fas t r espo n se r e giste r . t he for m ula for calculating the w ake - up period is as follows: wu t = w u t_ m ? 4 ? 2 ------------- - - ? m s ? 3 2 ? 768 the r c o s cillator freque n c y will c hange w ith temperature; s o, a periodic re c alibration is req u ired. the rc oscillator is automatically calibrated d u ring the power_up command and ex i t s from the shu t d o wn s t ate. t o e n a b le the r ecali b r a ti on f e atu r e , cal _ e n mus t be s et i n th e g l obal _ w ut _ confi g p r o pe r t y , a nd t he desi r e d calib r ation p e ri o d s h o u ld be s e l e ct e d via wu t _ c al _ pe r i o d[ 2 : 0 ] in t h e s a m e api p r o p e r t y . d u ri n g t he c a lib r a ti o n, the 32 k hz rc os c illator frequency is com p ared to the 30 mhz x t al and then adju s ted a c cordingl y . the calibration n ee ds t o s t a r t t he 3 0 mh z x t a l, w h ic h incr e ase s t he a v e r a g e cu r r e n t consu m ption ; so , a l o ng er cal _ period r e s u l t s in a l o w e r av er a g e c u r r e n t c o n s um p t io n . th e 32 khz x t al accur a cy is comprised of both the x t al p a r am e ter s a n d t he i nter n a l ci r c ui t . th e x t a l accur a c y c an be d efine d a s th e x t a l initi al e r r or + x t a l a gi ng + x t al temperature dri f t + detuning from the internal os c illator circuit. the error c aused by the internal circuit is typically less than 10 ppm. t a b le 15. wut s pecific c o mmands and properties api pro p erti e s de s cription re q uireme n t s/not e s global_wut_con f i g g l oba l wu t co nf igu r ation w ut_e n ? enable/disable wake up time r . wut _ lbd_en ? en a ble / dis a ble l ow b a tte r y detect me a s u r e me nt o n w ut i n t e rv a l. w ut_ldc_en: 0 = disab le low duty cy c le operation. 1 = r x ldc o p e r ation tre a te d a s w a k e u p s t a r t _ rx wut s t ate is used 2 = t x l dc o p e r a t ion t r e a t ed a s w a k e u p s t a r t _ tx w ut s t ate is u s ed ca l _en ?en a bl e cali b r a ti on o f t he 3 2 kh z rc os c i llator w u t _ c al _ per i o d [2 : 0 ] ? s e t s cali br ati o n p e r io d . global_wut_ m _1 5 _8 se t s h w wu t _m[1 5 : 8] w ut_m ? parameter t o set t he actual wakeup t ime. se e e q u a ti on abo ve. global _ wu t _m _ 7_0 se t s h w wut _ m[7:0] w ut_m ? parameter t o set t he actual wakeup t ime. se e e q u a ti on abo ve. global_ w ut_r se t s wut_r[4:0] se t s wut_s leep to choose wut s t a t e w ut_ r ? parame t er to s et the a c tual w a k eup time. se e e q u a ti on abo ve. w ut_sleep: 0 = go t o r e a d y s t a t e a f t er wut 1 = g o t o sl e e p s t at e a f te r wut globa l _wut_ l dc se t s f w i n t e r n a l wut _ ldc w ut_ldc ? parameter to s e t the ac t ual w akeup tim e . see equation in "8.2. l o w duty cycle mode (auto rx w ake - up ) " on p a ge 43.
http : //w ww.wenshing.com.tw ; http://www.rf.net.tw trw - hp9m2w datasheet p. 29 8.2. l o w duty cycle mode (auto rx w ake- up) t a ble 1 6 . wut related api co m mands a nd prope rties the low duty cycle (ldc) mode is implemented to a u tomatic a lly wa k e - up the re c ei v er to check if a valid signal is a v ailab l e or to enable the t r ans mitter to s end a p a c ket. it allo w s low a v erage current polling o peration by the trw - hp9m2w f o r w hich t h e w a k e - u p t im e r (w u t ) is u s e d. rx a nd t x ld c op e r a ti on m u s t b e s et vi a the globa l _wu t _confi g p r o p ert y w h e n settin g up t he wu t . t h e ld c w a k e - up p e ri od i s d eter m in ed b y the follo w ing formula: f i gure 18. rx and tx ldc s e quenc e s t he b asi c op e r a ti on of r x l d c m o d e i s s h ow n i n fig u r e 1 9 . the re c eiver periodi c ally w a k es i t s elf up to w ork on rx_s t a t e d u ri n g ld c mo de d u r ation . i f a v a li d p r e am b l e i s n o t d e t e c te d , a r e c e i v e e r r or is d e t e ct ed , or an en ti r e p a cket is not received, the receiver r e tur n s to t h e wut s t a t e (i. e ., r ea dy or s le e p) a t t he en d of l d c mo de dur a ti o n a n d r e mai ns i n th at mo de unti l t he b e gin n in g o f t he nex t w a k e - up p e ri o d. i f a v a li d p r ea m bl e o r syn c w o r d is d etect e d , th e r e ceive r d e lay s t he l d c m od e d ur a t i o n t o r e c e ive the entire p acke t . if a p acket is n o t r e ceived during two ldc mode d u r a tions, the r e ceiver r e tur n s to the wut s t a te at t h e l a st l dc mo de d u r a t ion u n til t he b eg in n ing of th e n e x t wake - u p p eri o d . f i gure 19. l ow duty c y cle mode for rx i n tx ldc m ode, th e t r a n s m itt er p e r i o dic a lly wakes i t self up to tran s mit a p a ck et t h at is in t he d a t a b u f f e r . if a comm a nd/prop e rty de s cription re q ui r eme n t s/not e s w ut interrupt enable int_ct l _enable i nte r r u p t ena bl e p ro p e r ty chip_int_s ta t u s_ e n ? enables chip s t atus i n t e r r u p t. int _ c t l_chip _ enab le c hi p i n t e r r up t e n abl e p r o per ty wu t_ en ?en ab les wut i n t e r r u p t. 32 k h z c l o c k source selec t ion global_clk_cfg clock con f iguration o p tions clk _ 32k _s e l [2:0] ? co n fi g u r in g th e so u rc e o f wu t . wut i n t e rrupt output g p io_pi n _ c f g hos t c an en a bl e i n t e r r u pt on w u t e x pi r e gp i o x _m o de[5:0] = 14 and ni r q _mod e [5 : 0] = 3 9 . r x /tx operation s t a r t_ rx/ t x s t a r t rx/t x w h e n wak e up tim er expi re s t a r t = 1.
http : //w ww.wenshing.com.tw ; http://www.rf.net.tw trw - hp9m2w datasheet p. 30 p a cket h a s b e en transm i t ted, nirq goes low if the o p tion is set in the int_ctl_enable propert y . a f ter transmitting, the t ran sm i t ter immedia t ely r etu r n s t o th e wu t s t at e an d s t a y s th e r e u n ti l th e n e x t wake - u p time e x pi r e s . 8.3. t emperature, battery v ol t age, and auxiliary adc the trw - hp9m2w family c ont ains an integrated auxiliary a d c for measuring internal b a ttery vol t age, an internal temperature senso r , or an external component over a gpio. the adc utili z es a sar ar c hitecture and a c hieves 1 1 - bi t r e s o lutio n. t he e f f e ctiv e nu m ber o f bi t s (e nob ) i s 9 bi t s. w h e n m eas u ri ng exter n a l com p o n en t s , t he in p u t v o l t a g e r a nge is 1 v , a n d t he c o n v e r s ion r a te is be tw e en 3 0 0 hz to 2 . 44 k hz. th e adc v al u e is r e a d b y fi r st s e n d i n g t h e ge t_ adc _ re a ding c o mma nd and e n a b li n g t h e in put s t h a t a r e d esi re d to b e r e a d : g pi o , ba tt e r y , o r tem p . t he temperature sensor a c curacy at 25 c is typically 2 c. co m ma nd s t r e am reply s tream p a r a mete rs ?? tempe r a ture_en 0 = do n o t perform a d c c o nversion o f temperature. t h is w i ll read 0 va l ue in rep l y temper a tur e. 1 = perform adc co n v e rs i on of tem p era t ure. this resu l t s in temp_ad c . t e mp (c) = temp _ adc[15:0] x 5 6 8/ 2 560 ? 2 9 7 ?? ba tte r y_vo l t age_ en 0 = do n ' t do adc c o nversi o n o f b a ttery vol t age, will r e ad 0 value i n re ply b a tte r y_adc 1 = do adc convers i on of b attery vol t age , resu l t s in b a tte r y_adc. vbatt = 3*b a tte r y_adc/1280 ?? adc_gpio_en 0 = do n ' t do adc c o nversi o n o n gpio, will re a d 0 v a lue in r e ply 1 = do adc convers i on of gpio, res u l t s in g p io_adc. v g pio = gpio_ad c /gpio_adc _ div wh e re gpio _ adc_div is d efined b y gp io_ a tt selectio n . ?? ad c _gpio_pi n [ 1 : 0] - se l ect gpiox p in. the p in m u st be set as i npu t. 0 = measure vo l t a ge of gpio0 1 = measure vo l t a ge of gpio1 2 = measure vo l t a ge of gpio2 get_ a dc_rea d ing co m mand 7 6 5 4 3 2 1 0 cmd 0 x ad c _ en 0 0 0 tempera ture_en ba tter y _ vo l t age_en adc _ gp i o _ en adc_ gp i o _p in [ 1 : 0 ] adc _ cfg udtime[3:0] gpio_a tt [3:0] get_adc_re a di n g r e ply 7 6 5 4 3 2 1 0 cts cts[7:0] gp i o _a d c gpio_adc[15:8] gp i o _a d c g pi o _a d c[7:0] b a tte r y_adc b a tte r y _ ad c [ 1 5 : 8] b a tte r y_adc b a tte r y_adc[7:0] t e mp _a d c te mp_adc[1 5: 8] t e mp _a d c temp_a d c[7:0] re s e r ved reser v ed re s e r ved reser v ed
http : //w ww.wenshing.com.tw ; http://www.rf.net.tw trw - hp9m2w datasheet p. 31 3 = measure vo l t a ge of gpio3 ?? udtime[7:4] - adc conversion t ime = sys_clk / 12 / 2^(udtime + 1 ) . defaul t s to 0xc if adc_cfg is 0. sel e cti n g s h orter c o nversion times will r e s u lt i n l o wer adc resol u t i on and l ong e r times will r e s u lt in h ig h er adc resol u t i on. gpio_ a t t [3:0] - se t s atten u ation of gpio i nput vol t age w h en vgp i o m e asure d . defa u l t s to 0 xc i f adc_ c f g i s 0. 0x0 = adc ran g e 0 to 0.8 v . gpio _ adc_div = 25 6 0 0x4 = adc ran g e 0 to 1.6 v . gpio _ adc_div = 12 8 0 ?? ?? 0x8 = adc ran g e 0 to 2.4 v . gpio _ adc_div = 85 3 .33 0x9 = adc ran g e 0 to 3.6 v . gpio _ adc_div = 42 6 .66 0xc = adc ran g e 0 to 3.2 v . gpio _ ad c_div = 640 ?? response ?? gpio_ad c [ 1 5: 0 ] - ad c v a lue of vol t age on gpio ?? ba t t er y_adc[15:0] - adc val u e o f b a ttery vol t age ?? temp_adc[15:0] - adc val u e of temper a t u re s e nsor v o l t a ge ?? r eser ved[7:0] - re se r ved for future use ?? r eser ved[7:0] - re se r ved for future use 8.4. l o w battery detector the low battery detector (lbd) is enab l ed and utilized as p art of the wake - u p - t i mer (w u t). the lbd function is not a v a ilab l e unl e s s th e wu t i s e n abl e d , b u t t he hos t mc u c an manually che c k the batte r y vol t age a n ytime with the auxiliary ad c . the lbd function is enabled in the global_ w ut_ c onfig a p i propert y . the battery vol t age will be c o m p a r e d a g ains t th e th r esh old e a c h tim e th e wu t e x pir e s . th e th r esh old fo r th e lb d f u ncti on i s se t i n globa l _low _ b a tt _ thresh . th e th r eshol d st e p s a r e i n i n c r em e n t s o f 50 m v , r an g in g f r o m a mi ni mu m of 1 . 5 v u p t o 3 . 05 v . t he a c cu ra cy of t he l bd is 3 %. th e l b d notificatio n c an b e c o nfig u r ed as a n inte r r u p t on the n ir q p i n o r e nab le d as a di r ec t fu nc ti on o n o n e o f t he gpios. 8.5. antenna diversity t o mitig a t e th e p r o b le m o f f r eq u e n cy - s el ectiv e fadi ng du e t o mu l ti p at h p r o p a g ation , s o m e tra n scei v er system s u s e a s c h em e k n own as a n t e n na div er sit y . in t his s c h em e, t w o a n t en n a s a r e u s e d . e a ch ti m e t h e t r a n s cei v er en te r s rx m o d e t he r eceiv e sig n a l stre n gt h f r o m e ac h a n ten na i s eval u ate d. t h i s evalu a tio n pr o c e s s t a k es pl ac e d u ri n g the p r e am b l e p o rtio n o f th e p ac k e t . t h e ante n n a wit h t he str o ng e s t r eceive d sign al i s the n use d fo r t he r e m ain d e r of that rx p a cket. the same antenna will also be used for the ne x t c orresponding tx p ac k et. this c hip fully suppor t s a nten na dive rs it y wit h an integ r ate d a nte n n a di v e rsit y c ont r o l alg o rith m. t h e r e qui r e d sig n al s nee d ed t o co nt ro l an e x t e r n al spdt r f swi t ch ( s u c h as a pin d io d e o r ga as switc h) a re avail a bl e on t he gpio x pi ns . t he op e r a ti on of t h e s e g pio s ig n als is p r ogr a m ma ble to a ll o w for di f fe re nt a n t e nn a di v e r sity a r c hi t e c t u r e s a n d c onfi g u r a t io n s. th e ant d iv[2:0] bi t s are found in the m odem_ant_div_contro l ap i p ro p e r t y d esc ri ptio ns a n d ena bl e t he a n t e n na di v e r sity m ode. th e g pio pi n s a re c a p a ble of s o u r c ing up to 5 ma o f c ur r e n t ; s o , it m ay be u s ed di r e c tly t o forward - bias a pin diode if desired. the antenna diver s ity algorithm will a u tomati c ally toggle back and forth b etw e e n t he a n t e nn as u nti l th e p acke t s t ar t s t o a r ri v e. t h e r ecom m end e d pr e am b l e l e ngt h fo r o p ti m a l a n t e nna sele c tion is 8 b ytes.

▲Up To Search▲

Price & Availability of TRW-HP9M2W

	To Download TRW-HP9M2W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .